1. Field of the Invention
The present invention relates to semiconductor memory devices and write masking methods, and more particularly, to a static random access memory (RAM) that reliably performs a write masking function.
2. Description of the Related Art
A static random access memory cell may be implemented using an inverter having a large driving capacity and an inverter having a small driving capacity connected to form a latch. A write bit line for writing data to the memory cell connects through a first pass transistor to the input terminal of inverter having the large driving capacity, and a read bit line for reading data from the memory cell connects through a second pass transistor to the output terminal of inverter having the large driving capacity. Each of the write bit line and the read bit line requires a single line. In an array, each row of memory cells has the gates of the first pass transistors connected to a single write word line and the gates of the second pass transistors connected to a single read word line. When a write word line is activated, the memory cells in the corresponding row are simultaneously connected to the respective write bit lines, which enables storage of values from the write bit lines in the memory cells. Accordingly, writing data to a single memory cell in a row requires write masking. Otherwise, undefined or incorrect data are written to the other memory cells in the same row.
One embodiment of the present invention provides a semiconductor memory device that reliably performs write masking. Another embodiment of the present invention provides a write masking method suitable for a semiconductor memory device.
In an exemplary embodiment of the present invention, a semiconductor memory device includes: a plurality of write bit lines, a plurality of write word lines, a plurality of write drivers, a plurality of MOS transistors, a plurality of latch circuits, and a plurality of precharge controllers.
Each of the write drivers is connected to one of the write bit lines, receives input data, a write enable signal and a write masking signal, outputs the input data when the write enable signal is activated and the write masking signal is deactivated, and does not output the input data when the write masking signal is activated.
Each of the MOS transistors is connected to between one of the latch circuits and one of the write bit lines and is gated by a signal applied to an associated one of the write word lines.
The plurality of latch circuits together with the plurality of MOS transistors form a plurality of memory cells. Each of the latch circuits includes a first inverter and a second inverter and is connected to one of the MOS transistors. The first inverter has a driving capacity larger than that of the second inverter.
Each of the precharge controllers is connected to one of the write bit lines, receives a precharge signal, and precharges the write bit line to the logic threshold voltage of the first inverter when the precharge signal is activated.
The present invention also provides a semiconductor memory device including a plurality of write bit lines; a plurality of write word lines; a plurality of write drivers; a plurality of first MOS transistors; a plurality of latch circuits; a plurality of precharge controllers; a plurality of read word lines; a plurality of second MOS transistors; and a plurality of output buffers. Each of the write drivers is connected to one of the write bit lines, receives input data, a write enable signal and a write masking signal, outputs the input data when the write enable signal is activated and the write masking signal is deactivated, and does not output the input data when the write masking signal is activated. Each of the first MOS transistors is connected between one of the latch circuits and one of the write bit lines and is gated by a signal applied to an associated one of the write word lines. Each of the latch circuits is connected to one of the first MOS transistors and one of the second MOS transistors, and the latch circuits together with the first and second MOS transistors constitute a plurality of memory cells. Each of the latch circuits includes first and second inverters, the first inverter having a larger driving capacity than does the second inverter. Each of the precharge controllers is connected to an associated one of the write bit lines, receives a precharge signal, and precharges the associated write bit line to the logic threshold voltage of the first inverter when the precharge signal is activated. Each of the second MOS transistors is connected between one of the latch circuits and one of the read bit lines and is gated by a signal applied to an associated one of the read word lines. Each of the output buffers is connected to one of the read bit lines and buffers data on the read bit line.
A write masking method in accordance with and embodiment of the invention operates on a semiconductor memory device including a plurality of write bit lines, a plurality of read bit lines, and a plurality of latch circuits. Each of the latch circuits stores data input via one of the write bit lines and outputs the stored data via one of the read bit lines. Each of the latch circuits includes a first inverter having a large driving capacity, and a second inverter having a small driving capacity. The output and input terminals of the first inverter are respectively connected to the input and output terminals of the second inverter. The first inverter inverts the input data. The write masking method includes: precharging the write bit lines to the logic threshold voltage of the first inverters for a predetermined time, electrically connecting a selected write bit line to the input terminal of one of the first inverters, and driving the selected write bit line at the input voltage level of the selected first inverter.
In the semiconductor memory device according to the present invention, memory cells are reliably masked in a write masking mode.